This invention relates to semiconductor processing, particularly to a shallow-trench-isolation structure and the method of forming a trench with rounded upper corners.
Modern integrated-circuit technology is capable of packing a large number of individual circuit-elements near the surface of a small silicon chip. The individual elements are connected according to the circuit design by metal lines. The metal lines are imbedded in a matrix of multiple layers of metal and dielectric material. Beneath the silicon-chip surface, the circuit-elements are isolated from each other by regions of silicon dioxide to prevent unwanted electrical current passage between the circuit-elements.
The silicon dioxide regions may be formed in two techniques well known in the art of semiconductor processing. The Local Oxidation of Silicon (LOCOS) process forms the dioxide regions by thermally oxidizing a portion of the chip surface not designated for active circuit devices; the Shallow Trench Isolation (STI) process forms the dioxide regions by removing silicon from a portion of the chip surface and refilling with silicon-dioxide material where the isolation is required.
Generally speaking, LOCOS is not suitable for integrated circuits that have critical dimension smaller than 0.25 μm because of the “bird's beak” effect that allows the thermally grown silicon-dioxide region to encroach into the adjacent area where active circuit elements are to be built and the stress-induced silicon defects associated with the thermal process. The successor to LOCOS is shallow trench isolation (STI).
In a STI structure, a relatively shallow trench is first etched into the silicon substrate, which is then refilled with an insulator material. Following a short thermal-oxidation step that forms a thin film of SiO2 on the trench walls and a refilling step that deposits a SiO2 film on the chip, the surface is planarized by CMP to complete the isolation structure.
Since the bird's beak is entirely eliminated in a STI structure, smaller isolation spacing between circuit elements is possible compared with a LOCOS structure. In addition, the field oxide in STI is fully recessed, offering the potential of a completely planar surface after the isolation-structure formation.
STI significantly shrinks the area needed to isolate circuit elements and it provides better planarity. From a processing point of view, however, the formation of a STI structure that fully realizes the advantages is a little more complicated. One of the challenges lie in providing void-free, seamless gap-fill by CVD and uniform planarization by CMP; another in providing properly rounded corners at the upper edges of the trench. In the current art, void-avoidance is accomplished by the combination of using a high-density-plasma CVD (HDP-CVD) process, which includes sputter-etching action, and forming trenches with slanted sidewalls.